The present invention relates to methods for making multi-dimensional integrated circuits that are field programmable.
Integrated electronic circuits (ICs) are usually fabricated with pre-specified devices and internal connections which are implemented during the manufacturing process. Moreover, once a fabrication process is specified for a particular IC, the process typically is not substantially altered unless major processing errors are identified. Any changes to the particular IC design have no accompanying changes to the fabrication process. This methodology is followed in custom or semi-custom application specific integrated circuit (ASIC) devices used in high volume, low cost applications.
The design and fabrication of custom or semi-custom ICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during the manufacturing phase. Further, should errors exist in the custom or semi-custom ICs, the design/fabrication cycle has to be repeated, further aggravating the time to market and engineering cost. As a result, ASICs serve only specific markets and are custom built for high volume and low cost applications.
Another type of semi custom device called a Gate Array customizes modular blocks at a reduced NRE cost by synthesizing the customer design using a software tool into the pre-defined sea of gates. Only the metallization is customized to place and route the design, reducing both the custom mask cost and time to solution. Shrinking transistor geometries and increasing levels of metal needed to connect gates have made this technique undesirable. The missing silicon level design verification results in multiple spins and lengthy design iterations. To reduce the turn around time some Gate Arrays provide fewer customizable metal levels which aggravate connectivity needed to place and route designs with timing closure. Some Gate Arrays, as disclosed in U.S. Pat. Nos. 4,240,094, 5,679,967, 5,986,319, 6,255,718 and 6,459,136, provide metal customization by connecting and/or disconnecting metal by directing pulsed laser energy. The laser process performed at wafer level incur product delivery delay and unpredictable wire to wire capacitance loading and current leakage that severely impact timing closure and signal integrity in the metal tracks.
In recent years there has been a move away from custom or semi-custom ICs towards field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. FPGA architectures are discussed in U.S. Pat. Nos. 4,609,986, 4,706,216, 4,761,768, 4,870,302, 4,873,459, 5,488,316, 5,343,406, 5,835,405, 5,844,422, 6,134,173, 6,239,613, 6,275,065, 6,448,808, and 6,515,511. These patents disclose specialized routing blocks to connect logic elements in FPGA's and macro-cells in PLD's. In all cases the routing block is programmed to define inputs and outputs for the logic blocks, while the logic block performs a specific logic function. They offer programmability at the point of use by the user. Off the shelf, generic Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA) products greatly simplify the design cycle. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to optimize silicon performance. The flexibility of this in field programmability is expensive in terms of silicon real estate, very slow in terms of performance, but reduces design cycle and upfront NRE cost to the designer.
FPGAs offer the advantages of low non-recurring engineering costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the more traditional ASIC approaches, but the volumes are unpredictable during early stages of the product life cycle. However, the conversion from an FPGA implementation to an ASIC implementation typically requires a complete redesign. Such redesign is undesirable in that the FPGA design effort is wasted. Anytime a design is mapped from an FPGA to a structured array platform, it is still a new design with a lengthy design cycle time at a high cost to the user.
Compared to PLD and FPGA, an ASIC has hard-wired logic connections, identified during the chip design phase, and need no configuration memory cells. This is a large chip area and cost saving for the ASIC. Smaller ASIC die sizes lead to better performance. A full custom ASIC also has customized logic functions which take less gate counts compared to PLD and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count PLD or FPGA. The trade-off is between time-to-market (PLD and FPGA advantage) versus low cost, higher performance and better reliability (ASIC advantage).
There is no convenient migration path from a PLD or FPGA used as a design verification and prototyping vehicle to the lower die size ASIC. All of the SRAM or Anti-fuse configuration bits and programming circuitry has no value to the ASIC. Programmable module removal from the PLD or FPGA and the ensuing layout and design customization is time consuming with severe timing variations from the original design.